Method for producing semi-insulating resistivity in high purity silicon carbide crystals

ABSTRACT

A method is disclosed for producing high quality semi-insulating silicon carbide crystals in the absence of relevant amounts of deep level trapping elements. The invention includes the steps of heating a silicon carbide crystal having a first concentration of point defect related deep level states to a temperature above the temperatures required for CVD growth of silicon carbide from source gases, but less than the sublimation temperature of silicon carbide under the ambient conditions to thereby thermodynamically increase the number of point defects and resulting states in the crystal, and then cooling the heated crystal to approach room temperature at a sufficiently rapid rate to maintain a concentration of point defects in the cooled crystal that remains greater than the first concentration.

[0001] This is a divisional application of copending Ser. No. 10/064,232filed Jun. 24, 2002.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to the inventions set forth incommonly assigned U.S. Pat. Nos. 6,218,680 (“the '680 patent”);6,396,080; 6,403,982; 6,639,247; and 6,507,046.

[0003] The present invention relates to semi-insulating silicon carbidesingle crystals, and in particular, relates to a method of forming highpurity semi-insulating silicon carbide single crystal substrates thathave intrinsic point defects and resulting deep level electronic statesin an amount greater than the net concentration of any compensatingshallow dopants (i.e., an amount greater than the uncompensated shallowdopants), and to maintain the semi-insulating quality of the siliconcarbide substrate during additional process steps of device manufacture.

[0004] As set forth in the '680 and related patents, it has beendiscovered that semi-insulating silicon carbide can be produced withoutthe use of vanadium as the dopant to create deep level states thatproduce the semi-insulating character.

[0005] Although vanadium can produce a semi-insulating silicon carbidecrystal, its presence has been observed to create a back-gating effect;i.e., the trapped negative charge on the vanadium acts as a grown-ingate in devices in which a vanadium-doped crystal is used as thesemi-insulating substrate. Thus, for a number of device considerations,vanadium is best avoided.

[0006] In the '680 patent and the related applications, asemi-insulating silicon carbide crystal is described that includes donordopants, acceptor dopants and intrinsic point defects that produce deeplevel states. When the concentration of intrinsic point defects exceedsthe difference between the concentration of donors and the concentrationof acceptors, the states resulting from intrinsic point defects canprovide semi-insulating characteristics in the functional absence ofvanadium; i.e., including a minimal presence that is less than thepresence that can affect the electronic properties of the crystal.

[0007] The requirements for and the advantages of semi-insulatingsubstrates, their use in devices, particularly microwave devices, andthe associated and particular requirements for silicon carbidesemi-insulating substrates are set forth in detail in the '680 patentand related applications, and are generally well understood in the artfrom a background standpoint. Thus, they will not be repeated in detailherein. For reference purposes, a relevant discussion is set forth inthe '680 patent at column 1, line 14 through column 3, line 33, which isincorporated entirely herein by reference.

[0008] To this discussion it should be added, however, that theever-increasing demand for wireless communication services, includinghigh bandwidth delivery of Internet access and related services, drivesa corresponding demand for devices and circuits that can support suchdelivery, which in turn calls for materials—such as semi-insulatingsilicon carbide—from which devices having the required capabilities canbe manufactured.

[0009] Accordingly, the '680 patent explains that superior microwaveperformance can be achieved by the fabrication of silicon carbide fieldeffect transistors (FETs) and related devices on high purity,vanadium-free semi-insulating monocrystalline silicon carbidesubstrates. As set forth in the '680 patent, the substrates derive theirsemi-insulating properties from the presence of intrinsic (point defectrelated) deep electronic states lying near the middle of the siliconcarbide bandgap. The intrinsic deep states generally arise during growthof a crystal boule at high temperatures from which substrate wafers arecut in a manner generally well understood in this art.

[0010] In devices that incorporate these substrates, and in order toprovide the appropriate low-loss RF performance, the substrate must actas a low-loss dielectric medium by continuously maintaining itssemi-insulating characteristics. In turn, the ability to maintainsemi-insulating behavior is dependent upon the total number of intrinsicdeep states in the substrate. In current practice, if the density of theintrinsic deep levels is not sufficiently high it has been observed inpractice that the semi-insulating characteristics of the substrate canbecome reduced or functionally eliminated when subsequent steps arecarried out on or using a semi-insulating silicon carbide wafer. Suchsteps include the growth of epitaxial layers at temperatures of about(for illustrative purposes) 1400° or above on the semi-insulatingsilicon carbide wafer. This in turn reduces the number of useful devicesthat can be formed on or incorporating the wafers.

[0011] Although the inventors do not wish to be bound by any particulartheory, it appears that when semi-insulating silicon carbide substratewafers of this type are subjected to process steps at temperatureswithin certain ranges, the subsequent processing can act as an annealthat reduces the number of point defects. This can be thought of in thepositive sense that a higher quality crystal is created, but it isdisadvantageous when the number of intrinsic point defects is the basisfor the semi-insulating character of the substrate wafer.

[0012] Stated differently, if kept within a particular temperature rangefor a sufficient time, the crystal equilibrium or near-equilibrium willshift to one in which the number of point defects is reduced; i.e., thecrystal becomes more ordered (fewer point defects) at lower temperaturesthan it was at higher temperatures, in a manner expected in accordancewith well-understood thermodynamic principles.

[0013] Accordingly, a need exists for silicon carbide substrate wafersthat incorporate the advantages set forth in the '680 patent, and thatcan maintain these advantages during subsequent manufacture of devicesand circuits on or incorporating the semi-insulating silicon carbidesubstrate wafers.

SUMMARY OF THE INVENTION

[0014] Accordingly, it is an object of the invention to producesemi-insulating resistivity in high purity silicon carbide crystals, andto do so in a manner that results in a silicon carbide crystals thatmaintain their semi-insulating characteristics during and aftersubsequent device processing and manufacture.

[0015] The invention meets this object with a method of producing highquality semi-insulating silicon carbide crystals in the absence ofrelevant amounts of deep level trapping elements. The method comprisesheating a silicon carbide crystal to a temperature above thetemperatures required for CVD growth of silicon carbide from sourcegases, but less than the temperatures at which disadvantageously highrates of silicon carbide sublimation occur under the ambient conditionsto thereby thermodynamically increase the concentration (i.e., numberper unit volume) of point defects and resulting states in the crystal;and then cooling the heated crystal to approach room temperature at asufficiently rapid rate to minimize the time spent in the temperaturerange in which the defects are sufficiently mobile to disappear or bere-annealed into the crystal to thereby produce a silicon carbidecrystal with a concentration of point defect states that is greater thanthe concentration of point defect states in an otherwise identicallygrown silicon carbide crystal that has not been heated and cooled inthis manner.

[0016] In another aspect, the invention is the semi-insulating siliconcarbide crystal made by the method of the invention.

[0017] In yet another aspect, the invention is a method of producingsemiconductor device precursors on semi-insulating substrates. In thisaspect the invention comprises heating a silicon carbide substrate waferto a temperature of at least about 2000° C., then cooling the heatedwafer to approach room temperature at a rate of at least about 30° C.per minute, and then depositing an epitaxial layer of a semiconductormaterial on the substrate wafer.

[0018] The foregoing and other objects and advantages of the inventionand the manner in which the same are accomplished will become clearerbased on the followed detailed description taken in conjunction with theaccompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a schematic diagram illustrating the temperature rangesreferred to in the detailed description and several different coolingrates; and

[0020]FIG. 2 is a plot of the change in capacitance against temperaturein degrees Kelvin as measured by deep level transient spectroscopy(DLTS).

[0021]FIG. 3 is a comparative set of three plots from electronparamagnetic resonance (EPR) evaluation of silicon carbide crystalsamples.

DETAILED DESCRIPTION

[0022] Although the inventors do not wish to be bound by any particulartheory, the nature of the invention can be best understood in athermodynamic sense. As noted above, one object of the invention is toavoid the use of vanadium to produce semi-insulating character insilicon carbide. Instead, the present invention creates a sufficientlylarge concentration of point defect states in the silicon carbide sothat the concentration remaining after normal semiconductor processingand device manufacture still exceeds the number necessary to producesemi-insulating character.

[0023] Those familiar with the nature of silicon carbide and the basisfor semi-insulating characteristics will recognize that there is nospecific number or concentration of point defects that meets thisrequirement. Instead, the goal is to minimize the concentration of otherdopants (including point defects) in the lattice that could contributeto conductive characteristics, and then exceed that concentration withthe concentration of items, in this case point defects and the resultingstates they create, that create the desired semi-insulatingcharacteristics.

[0024] Stated differently, in a compensated crystal the concentration ofpoint defects that produce the desired deep level states and theresulting semi-insulating characteristics must be greater than the netconcentration of the shallow compensating dopants. Thus, asemi-insulating compensated crystal of silicon carbide can have arelatively high concentration of both acceptor and donor atoms, providedthat the number of point defects is in excess of the difference betweenthose concentrations. This concentration of point defects can also beexpressed as the concentration needed to exceed any uncompensatedshallow dopants.

[0025] It has been generally found to be more efficient, however, tominimize the number of potentially compensating donor and acceptor atomsand thus minimize the number of point defects required to exceed therelevant numerical difference. For example (and for discussion purposesonly), if the concentration of donor atoms were 2E17 (2×10¹⁷ cm⁻³) andacceptor atoms 3E17 (3×10¹⁷ cm⁻³), the concentration of point defectswould have to be greater than 1E17 (i.e. 3E17 minus 2E17). Thus,minimizing the number (concentration) of donor and acceptor atoms is thepreferred, although not necessary, manner of carrying out the presentinvention, because it reduces the number of states that need to becreated to produce the semi-insulating character in the crystal.

[0026] In its broadest aspect, the invention is a method of producinghigh quality semi-insulating silicon carbide crystals in the absence ofrelevant amounts of deep level trapping elements. In this aspect theinvention comprises heating a silicon carbide crystal to a temperatureabove the temperature required for chemical vapor deposition (CVD)growth of silicon carbide from source gases, but less than thetemperature at which disadvantageously high rates of silicon carbidesublimation occur under the ambient conditions to therebythermodynamically increase the concentration of point defects andresulting states in the crystal.

[0027] The starting crystals are preferably of high purity and areproduced by a seeded sublimation technique such as is set forth in U.S.Pat. No. RE34,861 (reissued from U.S. Pat. No. 4,866,005) or asdiscussed in Mueller, Status of SiC Bulk Growth from an Industrial Pointof View, J. Crystal. Growth v. 211 No. 1 (2000) pp 325-332.

[0028] The method then comprises cooling the heated crystal to approachroom temperature at a sufficiently rapid rate to maintain aconcentration of point defects in the cooled crystal that remainsgreater than the first concentration.

[0029] Stated somewhat differently, the method comprises the step ofcooling the heated crystal to approach room temperature at asufficiently rapid rate to reduce the time spent in the temperaturerange in which the defects-including, but not limited to, those createdby the heating step—are sufficiently mobile to be re-annealed into thecrystal to thereby produce a silicon carbide crystal with aconcentration of point defect-related deep level states that is greaterthan the concentration of such states in an otherwise identically grownsilicon carbide crystal that has not been heated and cooled in thismanner.

[0030] In the most preferred embodiments, the crystal is heated to atemperature of between about 2,000° C. and 2,400° C. at atmosphericpressure. These temperatures provide a useful range at atmosphericpressure. At temperatures higher than 2400° C. the silicon carbide tendsto sublime at undeniably high rates and thus temperatures above 2400° C.are less favored or disadvantageous at atmospheric pressure.

[0031] It will be understood by those familiar with the physicalproperties of silicon carbide that sublimation can occur over arelatively wide range of high temperatures. At lower portions of thisrange, the rate of sublimation is small enough to be of little or noconcern. At higher portions of this range, however, the rate ofsublimation will be high enough to be disadvantageous. Accordingly, theupper temperature limit of the method of the invention will to someextent be bounded by the subjective degree of sublimation found to betroublesome in particular circumstances. As noted above, at atmosphericpressure, 2400° C. has been found to be a convenient upper limit, but isnot an absolute one.

[0032] The purpose of raising the temperature to 2000° C. or greater isa thermodynamic one: in a normally expected fashion, the entropy of thecrystal is higher at higher temperatures, and thus, more of the pointdefects and resulting states that can produce semi-insulating characterare present at higher temperatures. Additionally, those familiar withsilicon carbide and the thermodynamics of crystals will recognize thatas the temperature increases, additional types of states can exist thatdo not occur at lower temperatures. If the heated crystal is properlycooled in accordance with the present invention, these additional typesof states can be preserved and will contribute to the desiredsemi-insulating properties.

[0033] Accordingly, heating the crystals to these temperatures creates amore disordered crystal, and the invention freezes (in a relative sense)these desired states in the crystals as the crystal is returned to roomtemperature. The cooling step is significant because if the crystal isallowed to spend too much time in intermediate temperature ranges, suchas those above about 1400° C., the crystal will undergo theaforementioned annealing process, and can reach a different equilibriumor near-equilibrium condition in which the states disappear (or arefunctionally reduced to an irrelevant number) as the crystal becomesmore ordered.

[0034] With respect to the preferred upper limit of 2400° C., it will beunderstood by those familiar with silicon carbide and crystal growthtechniques that this is a practical limitation at atmospheric pressurerather than an absolute one. Stated differently, 2400° C. is a preferredupper temperature when using relatively typical equipment operating atatmospheric pressure. Those having the ordinary skill expected in thisfield could carry out the heating at higher temperatures without undueexperimentation, but would have to add additional equipment andtechniques such as incorporating an overlying silicon and carbonatmosphere or using some other high pressure technique to prevent thesublimation of silicon carbide that begins to occur in statisticallysignificant amounts at such higher temperatures.

[0035] Thus, the method of the invention heats the crystal to atemperature as high as practical to produce as many states as possiblein the crystal while avoiding or minimizing degradation or sublimationof the crystal.

[0036] During the heating step, the crystal is preferably maintained atthe elevated temperature for a period of at least about two minutes, aninterval that has practical and functional considerations. From apractical standpoint, it will take several minutes under mostcircumstances to heat the silicon carbide crystal to this temperature.From a functional standpoint, this also provides sufficient time for thecrystal to reach an equilibrium or near equilibrium condition withrespect to the states that are desirably generated. The heating time ispresently functionally best expressed as a time sufficient to obtain athermal equilibrium or near equilibrium in the crystal having thedesired number of states. It will be understood that the crystal doesnot need to reach a full equilibrium in the most proper or restrictedsense of that term, but the term is used herein to describe a conditionin which the crystal reaches a given temperature and is maintained therefor a time sufficient to develop the desired number of states.

[0037] The step of heating the crystal preferably comprises heating thecrystal in an induction heater, in which case the step of cooling thecrystal includes (at least) reducing the power to the induction coil.Induction heaters and their method of operation in semiconductormanufacture are generally well understood in the art and can beincorporated according to the invention without undue experimentation.Thus, as the particular induction heater is not critical to the claimedinvention, it will not be discussed in detail otherwise herein.Additionally, other types of heating can be used by those of ordinaryskill in this art and without undue experimentation.

[0038] Once the crystal has been heated for the desired period of timeat the temperature of 2000° C. or above, it is cooled in a manner thatavoids dwelling for any significant time period in the temperature rangewhere the defects are mobile enough to disappear or to be re-annealedinto the system. In presently preferred embodiments, a rate of coolingin excess of about 30° C. per minute appears to be preferred with a rateof 150° C. per minute appearing to be a useful upper limit.

[0039] It will be understood by those familiar with thermodynamics andthe heating and cooling of materials, particularly materials atrelatively high temperatures, that the rate of cooling need be neitherconstant nor exact throughout the entire cooling process. Stateddifferently, while the crystal is cooling, and particularly while it iscooling within temperature ranges where re-annealing can occur atsignificant rates, the rate of cooling should desirably range betweenthe 30° C. per minute and 150° C. per minute preferred limits. For theusual and well-understood thermodynamic reasons, the heat loss and thusthe rate of cooling will tend to be most rapid as the crystal cools fromthe highest temperatures and will tend to moderate as the crystalapproaches and reaches lower temperatures. In particular, once thecrystal is cooled below the temperature range in which re-annealingtakes place at significant rates, the rate of cooling can become slowerwithout any functional disadvantage. Accordingly, as an individualcrystal is cooled, the rate at which it cools can vary within the30°-150° C. per minute preferred range while still taking advantage ofthe method of the invention.

[0040] A rate of cooling that is too slow allows the crystal to spendtoo much time in the temperature range at which the states will heal andthe crystal become sufficiently ordered to reduce the number of statesbelow the number necessary to retain the semi-insulatingcharacteristics. Alternatively, cooling at an overly-rapid rate canproduce mechanical stresses in the crystal including fracturing if thethermal stress is sufficiently great.

[0041] In preferred embodiments the cooling step includes both passiveand active steps. As a first step, the power to the induction heater iseither reduced or turned off entirely. At the relatively hightemperatures to which the crystal has been heated, the initial heat lossis a radiation heat loss. As the temperature becomes lower, themechanisms of conduction and convection cooling take over. Accordingly,to further encourage and control the cooling rate, the heating chambercan be flooded with an inert gas, typically argon. Additionally, thethermal mass of the crystal and of the materials with which it is placedin contact can be used to help control the cooling rate. Consequently,three basic ways to control the rate of cooling include adjusting thepower to the induction coil (or to any other relevant heating mechanismwell understood in this art such as resistance heating); flowing acooling gas around and over the silicon carbide crystal; and controllingthe thermal mass of the crystal and its surroundings; i.e., such as theuse of a heat sink. Because these are thermodynamic conditions, they canbe addressed in a number of different ways that are not critical to theclaimed invention and can be carried out by those of ordinary skill inthis art without undue experimentation.

[0042] The preferred cooling rate of between about 30° and 150° C. perminute can be also expressed as cooling the crystal to about roomtemperature in less than about 70 minutes, or—at a more rapidpace—cooling the crystal to about room temperature in less than about 20minutes.

[0043] Because the invention provides a beneficial semi-insulatingsilicon carbide crystal, including substrate wafers, the method of theinvention can further comprise the steps of heating the silicon carbidesubstrate wafer to a temperature of about 2,000° C. (and preferably tobetween 2,000° and 2,400° C.), cooling the heated wafer to approach roomtemperature at a rate of at least about 30° C. per minute (andpreferably approaching 150° C. per minute), and then depositing one ormore epitaxial layers of semiconductor material on the substrate wafer.Because the advantage of silicon carbide often (although notexclusively) relates to its wide bandgap properties, in preferredembodiments, the step of depositing the epitaxial layer will comprisedepositing an epitaxial layer selected from the group consisting ofother wide bandgap semiconductors such as silicon carbide or Group IIInitrides using chemical vapor deposition (CVD) techniques. In the caseof silicon carbide, the step of depositing the epitaxial layer istypically carried out at temperatures greater than about 1,400° C. Asnoted above, in prior techniques steps carried out at such temperaturestended to reduce the number of defects to a point at which the substratewould no longer have appropriate semi-insulating characteristics.Because the invention provides a method for controllably increasing thenumber of point defects and resulting deep level states as compared to“as-grown” crystals, these later processing steps do not spoil thesemi-insulating character of the crystal even though some of the defectsare expected to heal.

[0044] Accordingly, in another aspect, the invention comprises the waferand epitaxial layer(s) produced by this aspect and embodiment of theinvention.

[0045] The invention can be carried out on substrate wafers or singlecrystal boules, with substrates being the preferred embodiment becausetheir large surface-to-volume ratio enables them to cool at therelatively rapid rates that are useful in the invention withoutsuffering undue or catastrophic thermal stress. Other than thispractical point, however, there is no conceptual difference between themanner in which the additional states can be created in a wafer versus aboule. Accordingly, the invention can also comprise the steps of heatinga silicon carbide boule to a temperature of at least about 2,000° C.,then cooling the heated boule to approach room temperature at the rateof at least about 30° C. per minute, then slicing a silicon carbidewafer from the boule and then depositing one or more epitaxial layers ofsemiconductor material on the sliced wafer.

[0046] In an alternative embodiment, the method can comprise the stepsof slicing the silicon carbide wafer from the single crystal boule, thenheating the sliced wafer to the temperature of at least about 2,000°degrees C. at atmospheric pressure, and then cooling the heated wafer toapproach room temperature at a rate of at least 30° C. per minute, andthereafter depositing the epitaxial layer(s) of semiconductor materialon the sliced wafer.

[0047] As known to those familiar with the preparation of substratewafers and the growth of epitaxial layers, the sliced silicon carbidewafer is generally not used immediately after having been sliced, butinstead is cleaned and polished to prepare a more favorable surface forepitaxial growth. The polishing and cleaning steps for semiconductormaterials in general and silicon carbide in particular are wellestablished in this art, can be practiced without undue experimentation,and will not be otherwise discussed in detail herein.

[0048] In either case, the invention further comprises the wafer and oneor more epitaxial layers, and can further comprise devices thatincorporate the wafer and epitaxial layers formed according to themethods of the embodiments of the invention.

[0049] The invention is not limited to use with any particular devices,but commonly used microwave devices that incorporate semi-insulatingsilicon carbide substrates include various types of field effecttransistors (FETs), metal oxide semiconductor field effect transistors(MOSFETs), junction field effect transistors (JFETs),metal-semiconductor field effect transistors (MESFETs), heterostructurefield effect transistors (HFETs), high electron mobility transistors(HEMTs), and DMOS transistors. Those familiar with semiconductor devicesand devices useful for microwave frequency operation will recognize thatthis list is neither limiting nor exhaustive. It is, however,illustrative of the advantages provided by the invention described andclaimed herein.

[0050]FIG. 1 schematically illustrates the temperature ranges and thecooling rates used in the present invention. Those familiar with thesetechniques will recognize that FIG. 1 is explanatory in nature ratherthan an exact representation of particular experiments.

[0051]FIG. 1 is a plot of temperature versus time. Three general sets oftemperatures are characterized. The uppermost line designated at 10represents the temperature, preferably 2,000° C. for silicon carbide,above which the desired number of point defects is produced in themanner according to the present invention. Stated differently, theinvention includes the step of heating the silicon carbide crystal tothe temperature represented by line 10 or higher.

[0052] The second highest line is designated at 12 and represents alower temperature (which will be understood as relative rather thanexact, but which in preferred embodiments is about 1200° C.) thattogether with the upper temperature line 10 defines a temperature range(represented by the arrow 11) within which the states created above thetemperature line 10 will be expected to heal if the crystal is allowedto remain in this temperature range for a period of time sufficient toapproach an equilibrium or a near equilibrium condition. Accordingly,the invention as described herein minimizes the time that the crystalspends in the temperature range 11 once the increased number of stateshas been produced. As noted above, maintaining the cooling rate atbetween about 30° C. and 150° C. per minute is particularly helpfulwhile the crystal is within the temperature range schematicallyillustrated at 11 in FIG. 1.

[0053] The third line designated at 14 represents room temperature (25°C., 298 K) and defines another temperature range (designated by thearrow 13) between room temperature and the temperature line 12. Thetemperature range symbolized by the arrow 13 represents temperaturesthat are still above room temperature, but within which the amount ofreordering that may occur is statistically insignificant to thesemi-insulating characteristics.

[0054] For any number of reasons, the crystal normally can be expectedto cool all the way to room temperature whether during pre-manufacture,storage, shipping or even use. It will be understood, however, thatprovided the crystal is heated to a temperature above that representedby the line 10, and then cooled sufficiently rapidly to a temperaturebelow the temperature represented by the line 12, the benefits of theinvention will be accomplished, regardless of whether room temperatureis ever reached.

[0055] Three cooling curves are schematically illustrated as the linesat 15, 16, and 17. Because FIG. 1's abscissa represents time, it will beunderstood that the line 15 represents the slowest rate of cooling,while the line 17 represents the most rapid. In this sense, the extendedcurve 15 illustrates that the crystal would spend a much greater periodof time in the temperature range designated by the arrow 11 as comparedto crystals following the cooling curves designated by the lines at 16or 17. Thus, the curve 15 schematically represents a prior art approach(intentional or unintentional) to cooling the crystal, while the lines16 and 17 schematically represent the more rapid cooling steps of thepresent invention. As noted previously, provided the cooling rate meetsthe functional aspects described herein, the rate need not be constant.

[0056]FIG. 2 illustrates that the desired high concentrations ofdeep-levels correlate with higher growth temperatures. FIG. 2 plots thechange in capacitance as measured by deep level transient spectroscopy(DLTS) against temperature. The higher amplitude (e.g. at 300 K) of thecrystal samples grown at higher temperatures (solid line) represents alarger concentration of deep levels as compared to a sample grown at alower temperature (dashed line).

[0057] Deep level transient spectroscopy is generally well understood inthe semiconductor arts and is a sensitive method used to study deeplevels in semiconductors. The method is based on the capacitance chargeof a reversed biased diode when deep levels emit their carriers afterthey have been charged by a forward bias pulse. The emission rate istemperature dependent and characteristic for each type of defect. Usingthe temperature dependence of the emission rate, the activation energyof a deep level can be determined. See, e.g. ASTM International Test No.F978-02, “Standard Test Method for Characterizing Semiconductor DeepLevels by Transient Capacitance Techniques.” Other techniques forevaluating the crystal can include capacitance versus voltage (CV)techniques, as well as electron paramagnetic resonance (EPR).

[0058]FIG. 3 is a comparative set of three plots from electronparamagnetic resonance (EPR) evaluation of silicon carbide crystalsamples. EPR is a well-understood technique for measuring certaincharacteristics of materials and is also known as electron spinresonance (ESR) or electron magnetic resonance (EMR). EPR represents theprocess of resonance absorption of microwave radiation by paramagneticions or molecules, with at least one unpaired electron spin and in thepresence of a magnetic field. In analyzing crystals according to thepresent invention, EPR is used to measure the number of chargesoccupying deep traps in the crystal bandgap. By measuring the change inabsorption of microwave energy within a continuously varying strongmagnetic field, EPR detects the number of unpaired spins of electroniccharges trapped at various defects in the crystal lattice. The EPRmeasurement does not, however, evict the charges from the traps, butmerely detects their presence, thus permitting repeated analysis of thesame sample.

[0059] The three plots of FIG. 3 represent (from left to right), asilicon carbide crystal grown conventionally, a silicon carbide crystalheated and cooled in the range of 30° C. per minute according to thepresent invention and a crystal heated and cooled in the range of 150°C. per minute according to the present invention.

[0060] Each of the sections of FIG. 3 is sized identically and themagnitude (arbitrary units) of the EPR signal of the carbon vacancy(V_(c))—i.e. one of the types of point defects that provides the statesthat in turn provide semi-insulating character—is proportional to thenumber of defect centers detected by the EPR. As known to those familiarwith EPR, the “g-factor” (or “g-value”) is characteristic of the type ofelectron trap and is related to the microwave frequency and the magneticfield strength. Accordingly, given that the sample sizes measured werethe same within expected margins of experimental error, the magnitude ofthe EPR line for the carbon vacancies (from the trough to the peak) isproportional to the concentration of defects in the sample. Thus, FIG. 3illustrates a significant increase in the number of carbon vacancies(and a resulting improvement in semi-insulating character) from theas-grown condition (left panel) to the process of the invention using a30° C. rate of cooling (middle panel) to the process of the inventionusing a 150° C. rate of cooling (right hand panel).

[0061] In the drawings and specification there has been set forth apreferred embodiment of the invention, and although specific terms havebeen employed, they are used in a generic and descriptive sense only andnot for purposes of limitation, the scope of the invention being definedin the claims.

That which is claimed is:
 1. A semi-insulating silicon carbide crystalmade by the method of: heating a silicon carbide crystal having a firstconcentration of point defect related deep level states to a temperatureabove the temperatures required for CVD growth of silicon carbide fromsource gases, but less than the sublimation temperature of siliconcarbide under the ambient conditions to thereby thermodynamicallyincrease the concentration of point defects and resulting states in thecrystal; and cooling the heated crystal to approach room temperature ata sufficiently rapid rate to maintain a concentration of point defectsin the cooled crystal that remains greater than the first concentration.2. A compensated silicon carbide crystal according to claim
 1. 3. Acompensated crystal according to claim 2 in which the most concentrateddopant is present in an amount of about 5E16 or less.
 4. Asemi-insulating silicon carbide crystal made by the method of: heating asilicon carbide single crystal to a temperature of at least about 2000°C. to thereby thermodynamically increase the number of point defects andresulting deep level states in the crystal; and cooling the heatedcrystal to approach room temperature at a sufficiently rapid rate tomaintain a concentration of point defects in the cooled crystal thatremains greater than the first concentration.
 5. A semi-insulatingsilicon carbide crystal according to claim 4 having a polytype selectedfrom the group consisting of the 3C, 4H, 6H, and 15R polytypes ofsilicon carbide.
 6. A wafer and epitaxial layer produced by the methodof: heating a silicon carbide substrate wafer to a temperature of atleast about 2000° C.; cooling the heated wafer to 1200° C. or less at arate of at least about 30° C. per minute; and depositing an epitaxiallayer of a semiconductor material on the substrate wafer.
 7. A wafer andepitaxial layer thereon formed by the method of heating a siliconcarbide boule to a temperature of at least about 2000° C.; cooling theheated boule to approach room temperature at a rate of at least about30° C. per minute; slicing a silicon carbide wafer from the boule; anddepositing an epitaxial layer of a semiconductor material on the slicedwafer.
 8. A device that incorporates the wafer and epitaxial layeraccording to claim
 7. 9. A device according to claim 8 selected from thegroup consisting of FET's, MOSFET's, JFET's, MESFET's, HFET's, HEMT's,DMOS FET's, extended drain MOSFET's; vertical DMOS transistors, andlateral DMOS transistors.
 10. A wafer and epitaxial layer thereon formedby the method of slicing a silicon carbide wafer from a single crystalsilicon carbide boule; heating the sliced wafer to a temperature of atleast about 2000° C.; cooling the heated wafer to approach roomtemperature at a rate of at least about 30° C. per minute; anddepositing an epitaxial layer of a semiconductor material on the slicedwafer.
 11. A device that incorporates the wafer and epitaxial layeraccording to claim
 10. 12. A device according to claim 11 selected fromthe group consisting of FET's, MOSFET's, JFET's, MESFET's, HFET's,HEMT's, DMOS FET's, extended drain MOSFET's; vertical DMOS transistors,and lateral DMOS transistors.